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ISL21032
Data Sheet September 28, 2009 FN6239.2
Precision 0.600V Low Voltage FGATM References
The ISL21032 FGATM voltage references are very high precision analog voltage references specifically designed to meet the rigorous performance requirements of high current, low voltage VRM and POL modules. Fabricated in Intersil's proprietary Floating Gate Analog technology, these references feature guaranteed performance over the -40C to +130C operating temperature range. Additional features include guaranteed absolute accuracy as low as 0.5% over the operating temperature range of -40C to +130C. Long-term stability is 10ppm/1,000Hrs. The absolute accuracy and thermal performance of the ISL21032 family are an ideal fit for the next generation of high current, low voltage VRM and POL modules.
Features
* Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V * Initial Accuracy Options @ +25C 1.0mV, 2.5mV, and 5.0mV * Absolute Accuracy Options Over Operating Temp Range 0.5% (3.0mV), 0.75% (4.5mV), and 1.0% (6.0mV) * Supply Voltage Range . . . . . . . . . . . . . . . . . . 2.7V to 5.5V * Low Quiescent Current . . . . . . . . . . . . . . . . . . . 12A typ. * Long Term Stability. . . . . . . . . . . . . . . . 10ppm/1,000Hrs. * Thermal Hysteresis . . . . . . . . . 100ppm @ TA = +170C * Source and Sink Current . . . . . . . . . . . . . . . . . . . . . . 7mA * ESD Protection. . . . . . . . . . . . . 5kV (Human Body Model) * Standard 3 Ld SOT-23 Packaging * Extended Temperature Range . . . . . . . . . -40C to +130C * Pb-Free (RoHS Compliant)
Pinout
ISL21032 (3 LD SOT-23 TOP VIEW)
VIN 1 3 VOUT 2 GND
Applications
* Low Voltage, High Current VRM and POL Modules * Accurate Reference for Low Voltage DC/DC Converters
Ordering Information
PART NUMBER (Note) ISL21032BPH306Z-TK* ISL21032CPH306Z-TK* ISL21032DPH306Z-TK* PART MARKING DEU DEV APE VOUT OPTION (V) 0.6 0.6 0.6 GRADE 0.5%@ DTA = 170C 0.75%@ DTA = 170C 1.0%@ DTA = 170C TEMP. RANGE (C) -40 to +130 -40 to +130 -40 to +130 PACKAGE (Pb-free) PKG. DWG. #
3 Ld SOT-23 T&R P3.064 3 Ld SOT-23 T&R P3.064 3 Ld SOT-23 T&R P3.064
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. FGA is a trademark of Intersil Corporation. Copyright Intersil Americas Inc. 2006, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL21032
Absolute Maximum Ratings
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V Max Voltage VOUT to GND (Note 1) ISL21032, VOUT = 0.6V . . . . . . . . . . . . . . . . . . . . . -0.5V to +1.6V Voltage on "DNC" Pins. . . No Connections Permitted to These Pins. ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Thermal Information
Thermal Resistance (Typical, Note 2) JA (C/W) 3 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 371.4 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile (Note 3). . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. For guaranteed specifications and test conditions, see Electrical Specifications. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
NOTES: 1. Maximum duration = 10s. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. Post-reflow drift for the ISL21032 devices will range from 100V to 1.0mV based on experimental results with devices tested in sockets and also on FR4 multi-layer PC boards. The design engineer must take this into account when considering the reference voltage after assembly.
Electrical Specifications (VOUT = 0.600V) Operating Conditions: VIN = 3.0V, IOUT = 0mA, COUT = 0.001F, TA = -40 to +130C,
unless otherwise specified. SYMBOL VOUT VOA PARAMETER Output Voltage VOUT Accuracy @ TA = +25C ISL21032B06 ISL21032C06 ISL21032D06 VOA VOUT Accuracy Over Op Temp Range (-40 < TA < +130C) ISL21032B06 ISL21032C06 ISL21032D06 VIN IIN VOUT/VIN VOUT/IOUT Input Voltage Range Supply Current Line Regulation Load Regulation +2.7V VIN +5.5V Sourcing: 0mA ISOURCE 7mA Sinking: -7mA ISINK 0mA VOUT/t VOUT/TA ISC VN NOTES: 4. Thermal Hysteresis is the change in VOUT measured @ TA = +25C after temperature cycling over a specified range, TA. VOUT is read initially at TA = +25C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25C. The difference between the initial VOUT reading and the second VOUT reading is then expressed in ppm. For TA = 170C, the device under is cycled from +25C to +130C to -40C to +25C. 5. Limits are established by full device characterization over temperature range and are not tested in production. 6. FGATM voltage reference long term drift is a logarithmic characteristic. Changes that occur after the first few hundred hours of operation are significantly smaller with time, asymptotically approaching zero beyond 2000 hours. Because of this decreasing characteristic, long-term drift is specified in ppm/1kHr. Long Term Stability (Note 6) Thermal Hysteresis (Note 4) Short Circuit Current (Note 5) Output Voltage Noise TA = +25C TA = +170C TA = +25C, VOUT tied to GND 0.1Hz f 10Hz -1.0 -2.5 -5.0 -3.0 -4.5 -6.0 2.7 12 50 20 20 10 100 50 30 80 CONDITIONS MIN TYP 0.600 +1.0 +2.5 +5.0 +3.0 +4.5 +6.0 5.5 25 200 70 70 MAX UNITS V mV mV mV mV mV mV V A V/V V/mA V/mA
1kHrs
ppm mA VP-P
ppm/
2
FN6239.2 September 28, 2009
ISL21032 Typical Performance Curves, ISL21032 Low Voltage Output Reference
VIN = 3.0V, IOUT = 0mA, TA = +25C Unless Otherwise Specified
20 18 16 UNIT 3 14 12 UNIT 2 10 8 6 4 2 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 UNIT 1 IIN (A) IIN (A) 14 13 12 11 +85C 10 9 8 7 6 2.5 -40C +25C
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
FIGURE 1. IIN vs VIN (3 REPRESENTATIVE UNITS)
FIGURE 2. IIN vs VIN - 3 TEMPS
0.6010 (NORMAILIZED TO 0.6V AT VIN = 3V)
0.60008 0.60006 0.60004 UNIT 3 0.60002 0.60000 0.59998 0.59996 0.59994 0.59992 2.5 UNIT 2 UNIT 1
0.6005
VOUT (V)
UNIT 2 0.5995
UNIT 3
0.5990
UNIT 1
0.5985 -40
VOUT (V)
0.6000
-15
10
35
60
85
110
135
3.0
3.5
TEMPERATURE (C)
4.0 VIN (V)
4.5
5.0
5.5
FIGURE 3. VOUT vs TEMP
FIGURE 4. LINE REGULATION
D VO (V) (NORMALIZED TO VIN = 3.0V)
125 100 75 50 25 0 -25 -50 -75 -100 -125 2.5 3.0 3.5 4.0 VIN 4.5 5.0 5.5 1ms/DIV DVIN = -0.3V -40C +85C +25C 100mV/DIV DVIN = +0.3V
FIGURE 5. LINE REGULATION - 3 TEMPS
FIGURE 6. LINE TRANSIENT RESPONSE, CL = 0nF
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FN6239.2 September 28, 2009
ISL21032 Typical Performance Curves, ISL21032 Low Voltage Output Reference
VIN = 3.0V, IOUT = 0mA, TA = +25C Unless Otherwise Specified (Continued)
0 DVIN = +0.3V CL = 500pF 100mV/DIV PSRR (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 1ms/DIV 10 100 1k 10k FREQUENCY (Hz) 100k 1M 10M 100nF LOAD 10nF LOAD NO LOAD 1nF LOAD
DVIN = -0.3V
FIGURE 7. LINE TRANSIENT RESPONSE, CL = 1nF
FIGURE 8. PSRR vs f vs CL
0.6 0.5 0.4 0.3 VOUT (mV) 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -7 -6 -5 -4 SINKING -3 -2 -1 0 1 2 3 4 5 6 OUTPUT CURRENT SOURCING 7 20s/DIV -40C +25C IL = -50A +130C 200mV/DIV 0.2
IL = +50A
FIGURE 9. LOAD REGULATION vs TEMP
FIGURE 10. LOAD TRANSIENT RESPONSE @ IL = 50A, CL = 1nF
DVIN = +7mA
DVIN = -7mA
1ms/DIV
3.2 3.0 VIN 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 VOUT, IIN = 10A 0.8 0.6 0.4 0.2 0.0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 TIME (ms)
FIGURE 11. LOAD TRANSIENT RESPONSE @ IL = 7mA, CL = 1nF
VIN AND VOUT (V)
100mV/DIV
FIGURE 12. TURN-ON TIME @ TA = +25C
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FN6239.2 September 28, 2009
ISL21032 Typical Performance Curves, ISL21032 Low Voltage Output Reference
VIN = 3.0V, IOUT = 0mA, TA = +25C Unless Otherwise Specified (Continued)
120 100 80 ZOUT () 100nF LOAD 60 40 20 0 1 10 100 1k 10k FREQUENCY (Hz)
NO LOAD 1nF LOAD 10nF LOAD 5V/DIV 100k 1M 10s/DIV
FIGURE 13. ZOUT vs f vs CL
FIGURE 14. VOUT NOISE
FGA Technology
The ISL21032 series of voltage references use the floating gate technology to create references with very low drift and supply current. Essentially the charge stored on a floating gate cell is set precisely in manufacturing. The reference voltage output itself is a buffered version of the floating gate voltage. The resulting reference device has excellent characteristics which are unique in the industry: very low temperature drift, high initial accuracy, and almost zero supply current. Also, the reference voltage itself is not limited by voltage bandgaps or zener settings, so a wide range of reference voltages can be programmed (standard voltage settings are provided, but customer-specific voltages are available). The process used for these reference devices is a floating gate CMOS process, and the amplifier circuitry uses CMOS transistors for amplifier and output transistor circuitry. While providing excellent accuracy, there are limitations in output noise level and load regulation due to the MOS device characteristics. These limitations are addressed with circuit techniques discussed in other sections.
Board Assembly Considerations
FGA references provide high accuracy and low temperature drift but some PC board assembly precautions are necessary. Normal Output voltage shifts of 100V to 1mV can be expected with Pb-free reflow profiles or wave solder on multi-layer FR4 PC boards. Precautions should be taken to avoid excessive heat or extended exposure to high reflow or wave solder temperatures, this may reduce device initial accuracy. Post-assembly x-ray inspection may also lead to permanent changes in device output voltage and should be minimized or avoided. If x-ray inspection is required, it is advisable to monitor the reference output voltage to verify excessive shift has not occurred. If large amounts of shift are observed, it is best to add an X-ray shield consisting of thin zinc (300m) sheeting to allow clear imaging, yet block x-ray energy that affects the FGA reference.
Special Applications Considerations
In addition to post-assembly examination, there are also other X-ray sources that may affect the FGA reference long term accuracy. Airport screening machines contain X-rays and will have a cumulative effect on the voltage reference output accuracy. Carry-on luggage screening uses low level X-rays and is not a major source of output voltage shift, although if a product is expected to pass through that type of screening over 100 times it may need to consider shielding with copper or aluminum. Checked luggage X-rays are higher intensity and can cause output voltage shift in much fewer passes, so devices expected to go through those machines should definitely consider shielding. Note that just two layers of 1/2 ounce copper planes will reduce the received dose by over 90%. The leadframe for the device which is on the bottom also provides similar shielding.
Board Mounting Considerations
For applications requiring the highest accuracy, board mounting location should be reviewed. Placing the device in areas subject to slight twisting can cause degradation of the accuracy of the reference voltage due to die stresses. It is normally best to place the device near the edge of a board, or the shortest side, as the axis of bending is most limited at that location. Obviously mounting the device on flexprint or extremely thin PC material will likewise cause loss of reference accuracy.
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FN6239.2 September 28, 2009
ISL21032
If a device is expected to pass through luggage X-ray machines numerous times, it is advised to mount a 2-layer (minimum) PC board on the top, and along with a ground plane underneath will effectively shield it from from 50 to 100 passes through the machine. Since these machines vary in X-ray dose delivered, it is difficult to produce an accurate maximum pass recommendation. frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth. Wideband noise is reduced by adding capacitor to the output, but the value should be limited to 1nF or less to insure stability.
Temperature Drift
The limits stated for output accuracy over-temperature are governed by the method of measurement. For the -40C to 130C temperature range, measurements are made at +25C and the two extremes. This measurement method combined with the fact that FGA references have a fairly linear temperature drift characteristic insures that the limits stated will not be exceeded over the temperature range.
Noise Performance and Reduction
The output noise voltage in a 0.1Hz to 10Hz bandwidth is typically 30VP-P. The noise measurement is made with a bandpass filter made of a 1 pole high-pass filter with a corner frequency at 0.1Hz and a 2-pole low-pass filter with a corner
VIN = 5V R = 200
2N2905
VIN ISL21032 VOUT 0.6V/50mA 0.001F GND
FIGURE 15. PRECISION LOW NOISE, LOW DRIFT, 0.6V, 50mA REFERENCE
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FN6239.2 September 28, 2009
ISL21032 Small Outline Transistor Plastic Packages (SOT23-3)
0.20 (0.008) M C L b C VIEW C
P3.064
3 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES SYMBOL MIN 0.035 0.001 0.035 0.015 0.012 0.003 0.003 0.110 0.083 0.047 MAX 0.044 0.004 0.037 0.020 0.018 0.007 0.005 0.120 0.104 0.055 MILLIMETERS MIN 0.89 0.013 0.88 0.37 0.30 0.085 0.08 2.80 2.10 1.20 MAX 1.12 0.10 0.94 0.50 0.45 0.18 0.13 3.04 2.64 1.40 NOTES 6 6 3 3 4 5 0.25 8 Rev. 1 11/06 NOTES: 1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC-74 and JEDEC MO178AB.
6 C L 1
5
4 C L E E1
A A1 A2 b b1
2
3
e e1 D C L C
c c1 D E E1
SEATING PLANE -C-
A
A2
A1
e e1 L
0.0374 Ref 0.0748 Ref 0.016 0.024 Ref 0.010 Ref 3 0.004 0.004 0 0.010 8
0.95 Ref 1.90 Ref 0.21 0.41
0.10 (0.004) C
L1 L2
0.60 Ref 0.25 Ref 3 0.10 0.10 0
WITH PLATING c
b b1 c1
N R R1
a
BASE METAL
4X 1 R1 R GAUGE PLANE SEATING PLANE L C 4X 1 VIEW C L1
3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only 8. Die is facing up for mold die and trim-form.
L2
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 7
FN6239.2 September 28, 2009

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